Advanced numerical modeling and hybridization techniques for third-generation infrared detector pixel arrays
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Infrared (IR) detectors are well established as a vital sensor technology for military, defense and commercial applications. Due to the expense and effort required to fabricate pixel arrays, it is imperative to develop numerical simulation models to perform predictive device simulations which assess device characteristics and design considerations. Towards this end, we have developed a robust three-dimensional (3D) numerical simulation model for IR detector pixel arrays. We used the finite-difference time-domain technique to compute the optical characteristics including the reflectance and the carrier generation rate in the device. Subsequently, we employ the finite element method to solve the drift-diffusion equations to compute the electrical characteristics including the I(V) characteristics, quantum efficiency, crosstalk and modulation transfer function. We use our 3D numerical model to study a new class of detector based on the nBn-architecture. This detector is a unipolar unity-gain barrier device consisting of a narrow-gap absorber layer, a wide-gap barrier layer, and a narrow-gap collector layer. We use our model to study the underlying physics of these devices and to explain the anomalously long lateral collection lengths for photocarriers measured experimentally. Next, we investigate the crosstalk in HgCdTe photovoltaic pixel arrays employing a photon-trapping (PT) structure realized with a periodic array of pillars intended to provide broadband operation. The PT region drastically reduces the crosstalk; making the use of the PT structures not only useful to obtain broadband operation, but also desirable for reducing crosstalk, especially in small pitch detector arrays. Then, the power and flexibility of the nBn architecture is coupled with a PT structure to engineer spectrally filtering detectors. Last, we developed a technique to reduce the cost of large-format, high performance HgCdTe detectors by nondestructively screen-testing detector arrays prior to their final hybridization onto expensive silicon read-out integrated circuit (ROIC) chips. The approach is to temporarily hybridize each candidate HgCdTe detector array to a standard reusable ROIC for complete screen testing. We tested the technique by temporarily hybridizing LPE grown HgCdTe test chips to fan-out boards and characterizing their performance.
Thesis (Ph.D.)--Boston University