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dc.contributor.authorEldridge, Schuyler
dc.date.accessioned2016-12-05T18:27:36Z
dc.date.available2016-12-05T18:27:36Z
dc.date.issued2016
dc.identifier.urihttps://hdl.handle.net/2144/19511
dc.description.abstractThe use of neural networks, machine learning, or artificial intelligence, in its broadest and most controversial sense, has been a tumultuous journey involving three distinct hype cycles and a history dating back to the 1960s. Resurgent, enthusiastic interest in machine learning and its applications bolsters the case for machine learning as a fundamental computational kernel. Furthermore, researchers have demonstrated that machine learning can be utilized as an auxiliary component of applications to enhance or enable new types of computation such as approximate computing or automatic parallelization. In our view, machine learning becomes not the underlying application, but a ubiquitous component of applications. This view necessitates a different approach towards the deployment of machine learning computation that spans not only hardware design of accelerator architectures, but also user and supervisor software to enable the safe, simultaneous use of machine learning accelerator resources. In this dissertation, we propose a multi-transaction model of neural network computation to meet the needs of future machine learning applications. We demonstrate that this model, encompassing a decoupled backend accelerator for inference and learning from hardware and software for managing neural network transactions can be achieved with low overhead and integrated with a modern RISC-V microprocessor. Our extensions span user and supervisor software and data structures and, coupled with our hardware, enable multiple transactions from different address spaces to execute simultaneously, yet safely. Together, our system demonstrates the utility of a multi-transaction model to increase energy efficiency improvements and improve overall accelerator throughput for machine learning applications.en_US
dc.language.isoen_USen_US
dc.subjectComputer engineeringen_US
dc.subjectRISC-Ven_US
dc.subjectHardware acceleratorsen_US
dc.subjectHardware/software co-designen_US
dc.subjectMulti-transaction computationen_US
dc.subjectNeural networksen_US
dc.subjectSimultaneous multithreadingen_US
dc.titleNeural network computing using on-chip acceleratorsen_US
dc.typeThesis/Dissertationen_US
dc.date.updated2016-11-05T01:08:08Z
etd.degree.nameDoctor of Philosophyen_US
etd.degree.leveldoctoralen_US
etd.degree.disciplineElectrical & Computer Engineeringen_US
etd.degree.grantorBoston Universityen_US


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