A design research study of the effects of process variation on the performance and functionality of a multi-input neural sensor (MINS) IC for neural signal recording
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In recent years, the effects of process variation have become increasingly more severe as technology has been scaling down in lithographic dimension. This problem also has affected the operation of the MINS IC (Multi-Input Neural Sensor) designed at Boston University by Dr. Lu Wang. This MINS chip was designed for use in both in-vitro and in-vivo applications of measuring and recording neural action potentials and local field potentials in the brains of animals. The MINS chip has been tested and is fully functional, however, with a serious problem of output level shifting from input-to-input due to process variation. This thesis will focus on the study of the effect of process variation on the MINS chip and a proposed method for process variation correction. The effect of process variation on the MINS chip is an extremely serious issue, given the large amount of gain required to sense and record neural signals, especially local field potentials, which have an input voltage of the order of 10-100 μV. The previous version of the printed circuit board designed to correct for process variation can center the output between the upper and lower rails by measuring the required column bias current independently for each of 256 inputs individually and storing these on an FPGA. However, this process variation correction procedure has jeopardized the ability to scan at the required rate in order to record action potentials (spikes). This thesis has two parts: The first part includes the study of the effects of process variation on the functionality of the 8HP MINS chip by doing Gaussian distribution analysis. The second part is the design of a new printed circuit board to increase the speed of the process variation correction procedure in scan mode, and as a goal, to center the output level in both stop mode and scan mode. The study of the effects of process variation on MINS utilizes circuit simulations with the IBM 8HP device models and design kit, using extracted models based on the MINS chip layout. According to the Monte Carlo sampling analysis, only 12 out of 200 samples are showing output level to be around center, with 65% of the samples having output voltage at upper and lower rails. What is more, as the study of 1000 cases shows, a column bias current of about 105uA and/or a bias voltage of 1.212 V, with 3σ to be 3.798uA and 0.131V respectively, is needed to center the output. A new developed version of the variation correction PCB has been designed and fabricated, utilizing a charge pump methodology to quickly charge up (or discharge) the large stabilization capacitor (4.7μF) placed on the Ibias0 node for stability, on the existing MINS PCB. Given that the Ibias0 current on MINS is only around 100μA, a large current of the order of 250-500mA is used in order to achieve the desired scan rate on the chip. A ping-pong approach is used, having two 4.7μF capacitors so that one can be readied while the other is being used for the testing. This PCB design also includes the needed controls with comparators and logic to terminate the charging/discharging operation at the exact correct voltage on the Ibias0 node, for each of the 256 inputs. On this new board, the required voltage at the Ibias0 node (Vbias0) to center the output, instead of Ibias0, will be measured and stored for each of 256 inputs in both stop mode and scan mode.
(Thesis: M.Sc.Eng.) PLEASE NOTE: Boston University Libraries did not receive an Authorization To Manage form for this thesis or dissertation. It is therefore not openly accessible, though it may be available by request. If you are the author or principal advisor of this work and would like to request open access for it, please contact us at email@example.com. Thank you.