The design of an 8-GHz synthesizer in the IBM 0.13μm 8HP technology and the study of the effects of process variation on its performance and functionality
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As semiconductor technology has been scaled down, increased variation in process parameters results in the variation of key device parameters, which will change the performance and operation of the integrated circuit. This MSEE thesis involves the study of the effects of process variation on the behavior of an 8-GHz clock generator (synthesizer) designed in the 0.13μm IBM 8HP BiCMOS technology, and the recommendation of changes that could be mader to the design that would make it more tolerant to process variation. The first part of this MS research project has involved the design of the phase-locked loop (PLL). The PLL contains a differential VCO (voltage-controller oscillator), a TPSC-DFF (True Single-Phase Clock D-Flip Flop) based 2/3/4 frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a logic control circuit and several buffers. since 8 GHz is a fairly high frequency for a clock generator in a 0.13μm technology and since high frequency circuit layouts inevitable degenerate the circuit performance, the frequency in the design part must necessarily be even higher than the specification. Therefore, this work combines the use of the known fastest architecture in every individual part. After completing the design of the synthesizer, it was simulated in Cadence, first with schematic-based models, using the IBM 8HP design kit, and was studies with statistical distributions utilized for key device parameters, as provided by the design kit. the layout of the circuit was completed and the simulations were redone using extracted models, based on the layouts, with the statistical parameter distributions included. According to Monte Carlo distribution simulation results, the most sensitive parameters were identified and analyzed. Based on those results, changes to the circuit have been proposed and studied, such as changes in device W and L, number of gate fingers nf, use of device multiplicity m, and/or changes to the basic circuit architecture to attempt to minimize the effects of process variation behavior functionality of the circuit.