Evaluating critical bits in arithmetic operations due to timing violations
Bahar, R. Iris
MetadataShow full item record
Citation (published version)Whang, S., Rachford, T., Papagiannopoulou, D., Moreshet, T., & Bahar, R. I. (2017, September). Evaluating critical bits in arithmetic operations due to timing violations. In High Performance Extreme Computing Conference (HPEC), 2017 IEEE (pp. 1-7). IEEE.
Various error models are being used in simulation of voltage-scaled arithmetic units to examine application-level tolerance of timing violations. The selection of an error model needs further consideration, as differences in error models drastically affect the performance of the application. Specifically, floating point arithmetic units (FPUs) have architectural characteristics that characterize its behavior. We examine the architecture of FPUs and design a new error model, which we call Critical Bit. We run selected benchmark applications with Critical Bit and other widely used error injection models to demonstrate the differences.