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dc.contributor.authorMoreshet, Talien_US
dc.contributor.authorWhang, Sungseoben_US
dc.contributor.authorRachford, Tymanien_US
dc.contributor.authorPapagiannopoulou, Dimitraen_US
dc.contributor.authorBahar, R. Irisen_US
dc.date.accessioned2018-02-12T15:51:13Z
dc.date.available2018-02-12T15:51:13Z
dc.date.issued2017-09-01
dc.identifier.citationWhang, S., Rachford, T., Papagiannopoulou, D., Moreshet, T., & Bahar, R. I. (2017, September). Evaluating critical bits in arithmetic operations due to timing violations. In High Performance Extreme Computing Conference (HPEC), 2017 IEEE (pp. 1-7). IEEE.
dc.identifier.urihttps://hdl.handle.net/2144/26956
dc.description.abstractVarious error models are being used in simulation of voltage-scaled arithmetic units to examine application-level tolerance of timing violations. The selection of an error model needs further consideration, as differences in error models drastically affect the performance of the application. Specifically, floating point arithmetic units (FPUs) have architectural characteristics that characterize its behavior. We examine the architecture of FPUs and design a new error model, which we call Critical Bit. We run selected benchmark applications with Critical Bit and other widely used error injection models to demonstrate the differences.en_US
dc.titleEvaluating critical bits in arithmetic operations due to timing violationsen_US
dc.typeConference materialsen_US
dc.identifier.doi10.1109/HPEC.2017.8091090
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: Not knownen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Engineeringen_US
pubs.organisational-groupBoston University, College of Engineering, Department of Electrical & Computer Engineeringen_US
pubs.publication-statusPublisheden_US


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