Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency
Bahar, R. Iris
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CitationT Moreshet, D Papagiannopoulou, A Marongiu, L Benini, M Herlihy, R Bahar. 2017. "Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency." International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors, but has a negative impact on performance and energy consumption. We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. The policy applies dynamic voltage scaling (DVS) (while keeping frequency fixed) based on the feedback provided by HTM, which makes it simple and generally applicable. Experiments on an embedded platform show our technique capable of 57% energy improvement compared to using voltage guardbands and an extra 21-24% improvement over existing state-of-the-art error tolerance solutions, at a nominal area and time overhead.