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dc.contributor.authorFarshchi, Farzaden_US
dc.contributor.authorValsan, Prathap Kumaren_US
dc.contributor.authorMancuso, Renatoen_US
dc.contributor.authorYun, Heechulen_US
dc.date.accessioned2018-04-05T18:27:41Z
dc.date.available2018-04-05T18:27:41Z
dc.identifierhttp://arxiv.org/abs/1707.05260v3
dc.identifier.citationFarzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun. "Deterministic Memory Abstraction and Supporting Multicore System Architecture."
dc.identifier.urihttps://hdl.handle.net/2144/28189
dc.description.abstractPoor timing predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform - the OS and hardware - guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.en_US
dc.subjectHardware architectureen_US
dc.subjectOperating systemsen_US
dc.subjectPerformanceen_US
dc.titleDeterministic memory abstraction and supporting multicore system architectureen_US
dc.typeArticleen_US
pubs.elements-sourcearxiven_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US


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