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dc.contributor.authorKloda, Tomaszen_US
dc.contributor.authorSolieri, Marcoen_US
dc.contributor.authorMancuso, Renatoen_US
dc.contributor.authorCapodieci, Nicolaen_US
dc.contributor.authorValente, Paoloen_US
dc.contributor.authorBertogna, Markoen_US
dc.coverage.spatialMontreal, Canadaen_US
dc.date2018-12-15
dc.date.accessioned2019-09-10T14:19:56Z
dc.date.available2019-09-10T14:19:56Z
dc.date.issued2019-04-15
dc.identifierhttps://ieeexplore.ieee.org/abstract/document/8743272
dc.identifier.citationTomasz Kloda, Marco Solieri, Renato Mancuso, Nicola Capodieci, Paolo Valente, Marko Bertogna. 2019. "Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems." Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Montreal, Canada, 2019-04-16 - 2019-04-18. https://doi.org/10.1109/RTAS.2019.00009
dc.identifier.issn1545-3421
dc.identifier.urihttps://hdl.handle.net/2144/37756
dc.description.abstractOne of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OS-transparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.en_US
dc.language.isoen_US
dc.publisherIEEEen_US
dc.relation.ispartofProceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
dc.subjectMulti-coreen_US
dc.subjectMemoryen_US
dc.subjectCacheen_US
dc.subjectHypervisoren_US
dc.subjectInvalidationen_US
dc.subjectInterferenceen_US
dc.subjectHigh performance embeddeden_US
dc.titleDeterministic memory hierarchy and virtualization for modern multi-core embedded systemsen_US
dc.typeConference materialsen_US
dc.description.versionAccepted manuscripten_US
dc.identifier.doi10.1109/RTAS.2019.00009
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US
pubs.publication-statusPublisheden_US
dc.identifier.mycv439978


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