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dc.contributor.authorFarshchi, Farzaden_US
dc.contributor.authorPrathap, Kumaren_US
dc.contributor.authorMancuso, Renatoen_US
dc.contributor.authorYun, Heechulen_US
dc.date.accessioned2019-09-10T18:34:47Z
dc.date.available2019-09-10T18:34:47Z
dc.date.issued2018-07-01
dc.identifier.citationFarzad Farshchi, Kumar Prathap, Renato Mancuso, Heechul Yun. 2018. "Deterministic Memory Abstraction and Supporting Multicore System Architecture." LIPIcs : Leibniz International Proceedings in Informatics, Volume 106, pp. 1 - 25. https://doi.org/10.4230/LIPIcs.ECRTS.2018.1
dc.identifier.issn1868-8969
dc.identifier.urihttps://hdl.handle.net/2144/37773
dc.description.abstractPoor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform-the OS and hardware-guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.en_US
dc.format.extentp. 1 - 25en_US
dc.language.isoen_US
dc.publisherSchloss Dagstuhl -- Leibniz-Zentrum fuer Informatiken_US
dc.relation.ispartofLIPIcs : Leibniz International Proceedings in Informatics
dc.subjectMulticore processorsen_US
dc.subjectReal-timeen_US
dc.subjectShared casheen_US
dc.subjectDRAM controlleren_US
dc.subjectLinuxen_US
dc.titleDeterministic memory abstraction and supporting multicore system architectureen_US
dc.typeArticleen_US
dc.description.versionAccepted manuscripten_US
dc.identifier.doi10.4230/LIPIcs.ECRTS.2018.1
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US
pubs.publication-statusPublisheden_US
dc.identifier.mycv439915


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