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dc.contributor.authorMancuso, Renatoen_US
dc.contributor.authorYun, Heechulen_US
dc.contributor.authorPuaut, Isabelleen_US
dc.coverage.spatialStuttgart, Germanyen_US
dc.date2019-03-27
dc.date.accessioned2020-05-07T15:44:11Z
dc.date.available2020-05-07T15:44:11Z
dc.date.issued2019-07-09
dc.identifier.citationRenato Mancuso, Heechul Yun, Isabelle Puaut. 2019. "Impact of DM-LRU on WCET: a Static Analysis Approach." Euromicro Conference on Real-Time Systems (ECRTS). Stuttgart, Germany, 2019-07-09 - 2019-07-12. https://doi.org/10.4230/LIPIcs.ECRTS.2019.17
dc.identifier.urihttps://hdl.handle.net/2144/40665
dc.description.abstractCache memories in modern embedded processors are known to improve average memory access performance. Unfortunately, they are also known to represent a major source of unpredictability for hard real-time workload. One of the main limitations of typical caches is that content selection and replacement is entirely performed in hardware. As such, it is hard to control the cache behavior in software to favor caching of blocks that are known to have an impact on an application's worst-case execution time (WCET). In this paper, we consider a cache replacement policy, namely DM-LRU, that allows system designers to prioritize caching of memory blocks that are known to have an important impact on an application's WCET. Considering a single-core, single-level cache hierarchy, we describe an abstract interpretation-based timing analysis for DM-LRU. We implement the proposed analysis in a self-contained toolkit and study its qualitative properties on a set of representative benchmarks. Apart from being useful to compute the WCET when DM-LRU or similar policies are used, the proposed analysis can allow designers to perform WCET impact-aware selection of content to be retained in cache.en_US
dc.language.isoen_US
dc.relation.ispartofEuromicro Conference on Real-Time Systems (ECRTS)
dc.rightsCopyright Renato Mancuso, Heechul Yun and Isabelle Puaut; licensed under Creative Commons License CC-BY.en_US
dc.rights.urihttp://creativecommons.org/licenses/by/3..0/
dc.subjectStatic cache analysisen_US
dc.subjectDynamic cache lockingen_US
dc.subjectStatic cache lockingen_US
dc.subjectWCET analysisen_US
dc.subjectCache profilingen_US
dc.subjectComputer systems organizationen_US
dc.titleImpact of DM-LRU on WCET: a static analysis approachen_US
dc.typeConference materialsen_US
dc.description.versionPublished versionen_US
dc.identifier.doi10.4230/LIPIcs.ECRTS.2019.17
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US
pubs.publication-statusPublisheden_US
dc.identifier.mycv535772


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Copyright Renato Mancuso, Heechul Yun and Isabelle Puaut; licensed under Creative Commons License CC-BY.
Except where otherwise noted, this item's license is described as Copyright Renato Mancuso, Heechul Yun and Isabelle Puaut; licensed under Creative Commons License CC-BY.