Show simple item record

dc.contributor.authorGracioli, Giovanien_US
dc.contributor.authorTabish, Rohanen_US
dc.contributor.authorMancuso, Renatoen_US
dc.contributor.authorMirosanlou, Rezaen_US
dc.contributor.authorPellizzoni, Rodolfoen_US
dc.contributor.authorCaccamo, Marcoen_US
dc.coverage.spatialStuttgart, Germanyen_US
dc.date2019-03-27
dc.date.accessioned2020-05-07T15:47:55Z
dc.date.available2020-05-07T15:47:55Z
dc.date.issued2019-07-09
dc.identifier.citationGiovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, Marco Caccamo. 2019. "Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms." 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Stuttgart, Germany, 2019-07-09 - 2019-07-12. https://doi.org/10.4230/LIPIcs.ECRTS.2019.27
dc.identifier.urihttps://hdl.handle.net/2144/40668
dc.description.abstractMultiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application.en_US
dc.language.isoen_US
dc.relation.ispartof31st Euromicro Conference on Real-Time Systems (ECRTS 2019)
dc.rights© G. Gracioli, R. Tabish, R. Mancuso, R. Mirosanlou, R. Pellizzoni, and M. Caccamo; licensed under Creative Commons License CC-BY.en_US
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/
dc.subjectMixed-criticality systemsen_US
dc.subjectSoC Heterogeneous platformsen_US
dc.subjectFPGAen_US
dc.subjectReal-time computingen_US
dc.titleDesigning mixed criticality applications on modern heterogeneous MPSoC platformsen_US
dc.typeConference materialsen_US
dc.description.versionPublished versionen_US
dc.identifier.doi10.4230/LIPIcs.ECRTS.2019.27
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US
pubs.publication-statusPublisheden_US
dc.identifier.mycv535777


This item appears in the following Collection(s)

Show simple item record

© G. Gracioli, R. Tabish, R. Mancuso, R. Mirosanlou, R. Pellizzoni, and M. Caccamo; licensed under Creative Commons License CC-BY.
Except where otherwise noted, this item's license is described as © G. Gracioli, R. Tabish, R. Mancuso, R. Mirosanlou, R. Pellizzoni, and M. Caccamo; licensed under Creative Commons License CC-BY.