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dc.contributor.authorRoozkhosh, Shahinen_US
dc.contributor.authorMancuso, Renatoen_US
dc.coverage.spatialSydney, Australiaen_US
dc.date2020-02-14
dc.date.accessioned2020-05-07T15:53:05Z
dc.date.available2020-05-07T15:53:05Z
dc.date.issued2020-04-21
dc.identifier.citationShahin Roozkhosh, Renato Mancuso. 2020. "The Potential of Programmable Logic in the Middle: Cache Bleaching." IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Sydney, Australia, 2020-04-21 - 2020-04-24.
dc.identifier.urihttps://hdl.handle.net/2144/40671
dc.description.abstractConsolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware re-designs, and by proposing software-only solutions to mitigate performance interference. Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.en_US
dc.language.isoen_US
dc.titleThe potential of programmable logic in the middle: cache bleachingen_US
dc.typeConference materialsen_US
dc.description.versionAccepted manuscripten_US
pubs.elements-sourcemanual-entryen_US
pubs.notesEmbargo: No embargoen_US
pubs.organisational-groupBoston Universityen_US
pubs.organisational-groupBoston University, College of Arts & Sciencesen_US
pubs.organisational-groupBoston University, College of Arts & Sciences, Department of Computer Scienceen_US
pubs.publication-statusPublisheden_US
dc.identifier.mycv535788


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