Boura, Jihad M.2025-04-172025-04-171998https://hdl.handle.net/2144/50113[An algorithm for test generation for combinatorial VLSI circuits under massively observable conditions is developed. The algorithm provides a means of determining single and multiple test sets that can be used for circuit verification under the single stuck-at fault model. The algorithm is based on analyzing the logical functionality of each node in the circuit. The new methodology differs substantially from all current approaches. Current techniques execute a topological search algorithm to control internal nodes and propagate their state to an output pin. Our technique transforms the test-generation problem into a logic minimization process by defining a logic function on the set of covering cubes.]en-USThis work is being made available in OpenBU by permission of its author, and is available for research purposes only. All rights are reserved to the author.Electrical engineeringComputer and system engineeringThesis/Dissertation