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    Evaluating memory subsystem of configurable heterogeneous MPSoC

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    Date Issued
    2018-05-01
    Author(s)
    Bansal, Ayoosh
    Tabish, Rohan
    Gracioli, Giovani
    Mancuso, Renato
    Pellizzoni, Rodolfo
    Caccamo, Marco
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    Permanent Link
    https://hdl.handle.net/2144/37758
    Version
    Accepted manuscript
    Citation (published version)
    Ayoosh Bansal, Rohan Tabish, Giovani Gracioli, Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo. 2018. "Evaluating Memory Subsystem of Configurable Heterogeneous MPSoC." Proceedings of the Operating Systems Platforms for Embedded Real-Time applications. Operating Systems Platforms for Embedded Real-Time applications
    Abstract
    This paper presents the evaluation of the memory subsystem of the Xilinx Ultrascale+ MPSoC. The characteristics of various memories in the system are evaluated using carefully instrumented micro-benchmarks. The impact of micro-architectural features like caches, prefetchers and cache coherency are measured and discussed. The impact of multi-core contention on shared memory resources is evaluated. Finally, proposals are made for the design of mixed-criticality real-time applications on this platform.
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    • CAS: Computer Science: Scholarly Papers [186]
    • BU Open Access Articles [3664]


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