Flexible communication primitives for diverse deployment scenarios of hardware operating systems for FPGAs
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Citation
Abstract
Communication capabilities of FPGAs, combined with programmability in hardware (reconfigurable logic) and software (soft-processors), often provide FPGAs a competitive edge over alternate technologies where communication requirements are highly demanding. The problem lies in not being able to harness these capabilities efficiently due to the fact that in the current FPGA hardware-development ecosystem, entire hardware stacks must often be rebuilt or reworked, even for minor changes in the application or target device. Existing frameworks, like FPGA-based NICs or hardware OS (hOS) shells reduce development complexity by connecting IP blocks needed to support core functionality, but limitations with these shells include having tightly coupled IP blocks, fixed overheads, unique interfaces, and vendor-specific IP and devices. These require custom host-side drivers and libraries and are limited to certain configurations. In this thesis we explore hardware architectures and design decisions to generate flexible communication primitives as a part of developing a loosely-coupled vendor-agnostic hOS generator. These communication primitives include the network and PCIe subsystems, as well as flexible intra-subsystem communication support implemented using soft-processors and memory subsystems with arbitration. We show that developing such highly configurable communication primitives for hOS generators saves FPGA resources and reduces implementation efforts whether porting to different devices or targeting various configurations. The first contribution is developing highly configurable and parameterized open-source network communication primitives and integrating them into a vendor-agnostic hOS generator (DISL). Users of DISL can then use a single configuration script to generate various configurations of network subsystems by selecting required modules from different PHYs, MIIs, MACs, Ethernet/Network/Transport layer blocks, interfaces, target configurations, DMA and memory devices, interconnects and arbitration options. We have also developed an extensive C library for network subsystem Mplane control using a RISC-V soft-processor. The second contribution involves the security and routing of the hOS communication primitives. For this we developed an eBPF ISA compliant CPU core called VeBPF (Verilog eBPF). We developed a novel many-core architecture using this VeBPF core as the PE (Processing Element) to implement eBPF rules for network firewall and routing. This is optimized for low resource usage for IoT target configurations. The third contribution is a heterogeneous simulation framework for the network subsystem using Python, Cocotb, Icarus Verilog and GTKWAVE for simulating complex network packet interactions with the various subsystems of DISL and externalapplications. This includes an automatic-testing framework for development and further advancement of the VeBPF CPU core. C libraries are used for real-time debugging of the packet processing. We demonstrate the flexibility and portability of the communication primitives by porting them to different FPGA boards with different PHYs, MIIs, MACs, interfaces and throughput. This is done using a single DISL configuration script and settingup eBPF rules for network packet processing in different FPGAs using the VeBPF many-core architecture.
Description
2025
License
Attribution 4.0 International