Evaluating memory subsystem of configurable heterogeneous MPSoC
Files
Accepted manuscript
Supplemental materials (from published version)
Date
2018-05-01
DOI
Authors
Bansal, Ayoosh
Tabish, Rohan
Gracioli, Giovani
Mancuso, Renato
Pellizzoni, Rodolfo
Caccamo, Marco
Version
Accepted manuscript
OA Version
Citation
Ayoosh Bansal, Rohan Tabish, Giovani Gracioli, Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo. 2018. "Evaluating Memory Subsystem of Configurable Heterogeneous MPSoC." Proceedings of the Operating Systems Platforms for Embedded Real-Time applications. Operating Systems Platforms for Embedded Real-Time applications
Abstract
This paper presents the evaluation of the memory subsystem of the Xilinx Ultrascale+ MPSoC. The characteristics of various memories in the system are evaluated using carefully instrumented micro-benchmarks. The impact of micro-architectural features like caches, prefetchers and cache coherency are measured and discussed. The impact of multi-core contention on shared memory resources is evaluated. Finally, proposals are made for the design of mixed-criticality real-time applications on this platform.