On the interplay of computation and memory regulation in multicore real-time systems
Files
Accepted version
Date
2022-07-05
DOI
Authors
Hoornaert, Denis
Ghaemi, Golsana
Bastoni, Andrea
Mancuso, Renato
Caccamo, Marco
Corradi, Giulio
Version
Accepted manuscript
OA Version
Citation
D. Hoornaert, G. Ghaemi, A. Bastoni, R. Mancuso, M. Caccamo, G. Corradi. 2022. "On the Interplay of Computation and Memory Regulation in Multicore Real-Time Systems" Proceedings of the 16th Operating Systems Platforms for Embedded Real-Time applications Workshop (OSPERT 2022).
Abstract
The ever-increasing demand for high performance in the time-critical embedded domain has pushed the adoption of powerful yet unpredictable heterogeneous Systems-on-a-Chip. The shared memory subsystem, which is known to be a major source of unpredictability, has been extensively studied, and many mitigation techniques have been proposed. Among them, performance-counter-based regulation techniques have seen widespread adoption. However, the problem of combining performance-based regulation with time-domain isolation has not received enough attention.
In this article, we discuss our current work-in-progress on
SHCReg (Software Hardware Co-design Regulator). First, we assess the limitations and benefits of combined CPU and memory budgeting. Next, we outline a full-stack hardware/software codesign architecture that aims at improving the interplay between CPU and memory isolation for mixed-criticality tasks running on the same core.