A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic
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Published version
Date
2021-07-30
Authors
Hoornaert, Denis
Roozkhosh, Shahin
Mancuso, Renato
Version
OA Version
Citation
D. Hoornaert, S. Roozkhosh, R. Mancuso. 2021. "A Memory Scheduling Infrastructure for Multi-Core Systems with Re-Programmable Logic." 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). 2021-07-05 - 2021-07-09. https://doi.org/10.4230/LIPIcs.ECRTS.2021.2
Abstract
The sharp increase in demand for performance has prompted an explosion in the complexity of modern multi-core embedded systems. This has led to unprecedented temporal unpredictability concerns in Cyber-Physical Systems (CPS). On-chip integration of programmable logic (PL) alongside a conventional Processing System (PS) in modern Systems-on-Chip (SoC) establishes a genuine compromise between specialization, performance, and reconfigurability. In addition to typical use-cases, it has been shown that the PL can be used to observe, manipulate, and ultimately manage memory traffic generated by a traditional multi-core processor. This paper explores the possibility of PL-aided memory scheduling by proposing a Scheduler In-the-Middle (SchIM). We demonstrate that the SchIM enables transaction-level control over the main memory traffic generated by a set of embedded cores. Focusing on extensibility and reconfigurability, we put forward a SchIM design covering two main objectives. First, to provide a safe playground to test innovative memory scheduling mechanisms; and second, to establish a transition path from software-based memory regulation to provably correct hardware-enforced memory scheduling. We evaluate our design through a full-system implementation on a commercial PS-PL platform using synthetic and real-world benchmarks.
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License
© Denis Hoornaert, Shahin Roozkhosh, and Renato Mancuso; licensed under Creative Commons License CC-BY 4.0.