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dc.contributor.authorBestavros, Azeren_US
dc.contributor.authorLiu, Yueh-Linen_US
dc.date.accessioned2012-05-17T16:53:28Z
dc.date.available2012-05-17T16:53:28Z
dc.date.issued1995-06-06
dc.identifier.citationBestavros, Azer; Liu, Yueh-Lin. "Simulation of Hardware Dynamic Scheduling on the DLX Architecture“, Technical Report BUCS-1995-013, Computer Science Department, Boston University, June 6, 1995. [Available from: http://hdl.handle.net/2144/3772]
dc.identifier.urihttps://hdl.handle.net/2144/3772
dc.descriptionThis technical report is available only in HTML format from http://cs-www.bu.edu/faculty/best/crs/cs550/yueh/dlxsim.htmlen_US
dc.description.abstractWe describe our extention of the existing DLX simulator (DLXsim), available from the University of California at Berkeley, which allows the simulation of two hardware dynamic scheduling techniques. There are two DLXsim-like interactive simulators developed as part of this project. DLXscore simulates the operation of a DLX architecture equipped with scoreboarding hardware. DLXscore provides the status of instructions, scoreboard tables, and statistics. DLXtomasulo simulates the operation of a DLX architecture equipped with a hardware implementation of Tomasulo's algorithm. DLXtomasulo provides the status of instructions, reservation stations, and statistics. Both programs allow the user to configure the number of functional units and the latency of floating point operations.en_US
dc.language.isoen_US
dc.publisherBoston University Computer Science Departmenten_US
dc.relation.ispartofseriesBUCS Technical Reports;BUCS-TR-1995-013
dc.titleSimulation of Hardware Dynamic Scheduling on the DLX Architectureen_US
dc.typeTechnical Reporten_US


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